The present invention generally relates to semiconductor devices which use a graded band gap structure to promote the injection of holes or electrons at one interface of an insulator under moderate electric field conditions while, simultaneously, electron or hole injection from the opposite interface is blocked. More particularly, the present invention, in a preferred embodiment, relates to a graded oxide metal-silicon dioxide-silicon (MGOS) semiconductor structure which is useful in performing a memory function.
Semiconductor memory devices in various configurations are known in the art. One such device, known as a beam addressable MOS, employs a metal-oxide-semiconductor structure, including a PN junction, wherein charges are stored in the structure by writing with an electron beam. Readout is also performed with an electron beam, but at a lower current level. The readout is not totally destructive in that upwards of 10 readouts can be performed before the charge in a memory cell must be renewed. The advantage of this device is that very high memory densities can be achieved. Among the disadvantages, however, are the requirement for an electron beam with a high vacuum, precision electron optics and deflection circuitry which result in a high cost.
FET memory devices are also known in the art. One such device employs a MI.sub.1 I.sub.2 S structure wherein I.sub.1 and I.sub.2 denote first and second insulator layers. The I.sub.1 I.sub.2 interface may include a metallic impurity which provides a well-defined electron trapping region. The presence or absence of trapped electrons in this region is used to define a memory function either by different values of capacitance of the structure or by monitoring the value of source-drain current as affected by the trapped electron charges in the presence of suitable-applied gate voltages. Metallic impurities are not always required at the I.sub.1 I.sub.2 interface as the same effect can be realized by using two different kinds of insulators. For example, one such known device employs a MNOS structure where a thin oxide film is first formed on a silicon substrate, and over this thin oxide film is laid a much thicker silicon nitride film. In this structure, electrons or holes are trapped in the silicon nitride layer. This particular structure has the advantage, when compared with the beam addressable MOS structure, of requiring much simpler equipment for performing the reading and writing operations in the memory device. There is a disadvantage associated with this particular structure, however, and that relates to the thin oxide layer. This oxide layer must be quite thin, on the order of about 20 A thick, in order to allow tunneling of the electrons or holes from the Si substrate. Reliability problems have been encountered with memory devices with this thin tunnel oxide layer because of the high fields across it during operation.